Differential phase shift keying (DPSK), a common form of phase modulation conveys data by changing the phase of carrier wave. In Phase shift keying, High state contains only one cycle but DPSK contains one and half cycle. Figure illustrates PSK and DPSK Modulated signal by 10101110 pulse sequence

DPSK & PSK modulated signals

High state is represented by a M in modulated signal and low state is represented by a wave which appears like W in modulated signal DPSK encodes two distinct signals of same frequency with 180 degree phase difference between the two. This experiment requires two 180 degree out of phase carrier and modulating signals. Sine wave from oscillator is selected as carrier signal. DSG converts DC input voltage into pulse trains. These pulse trains are taken as modulating signals. In actual practice modulating signal is digital form of voice or data. Sine wave is selected as carrier and 180 degree phase shift is obtained using Opamp as shown in figure below. Different methods are used to demodulate DPSK. The analog scheme is the PLL (Phase Locked loop).

The lead and lag carrier signals

DPSK Modulation: 

         In DPSK, during HIGH state of the modulating signal f_lead signal is allowed to pass and during LOW state of the modulating signal f_lag signal is allowed to pass.  Figure below shows DPSK [10] modulator circuit. The Opamp is tied in the inverting amplifier mode.  The closed loop voltage gain of the Opamp is given by  

                       R_F +r_{DS (on) 3}     

A_V(CL)  =   - ---------------------

                      R_I + r_{DS (on) 1,2}

  Where       r_{DS (on) 3}   is the drain- source resistance of Q3 FET

                   r_{DS (on) 1,2}  is drain-resistance of  the conducting FET(Q1 or Q2)

The drain source resistance is of the order of 100Ω which is very small compared to RF and RI. Hence                  

                      R_F         

A_V(CL)  =   -  ------

                       R_I

DPSK Modulator Circuit

 DPSK Demodulation:

DPSK Demodulation [12,13 & 14]is done with PLL IC 565[3 4 5]. DPSK [10] signal is given as input at DPSK input terminal of PLL as shown in the figure below.
A capacitor C is connected between pin7 and power supply forms first order low pass filter with an internal resistance 3.6KW, The capacitor C should be large enough to eliminate variations in the demodulated output voltage in order to stabilize the VCO frequency. The cut-off frequency of Low pass filter is made equal to carrier frequency. The cutoff frequency of low pass filter is given by 

              1

fH    =   -------------

          2pRC

 R = 3.6KW, fH = 18.7KHz

 The value of C designed by

             1

 C  =   -------------

          2pRfH 

             1

 C  =   -------------------          =  2.3nF

        2px3.6Kx18.7K 

C selected is 3nF

DPSK Demodulator Circuit

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