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MT 8870 DTMF decoder:
IC MT8870/KT3170 serves as DTMF
decoder. This IC takes
DTMF signal coming via telephone line and converts that signal
into respective BCD number. It uses same oscillator frequency
used in the remote section so same crystal oscillator with
frequency of 3.85M Hz is used in this IC.
Working of
IC MT8870:
The MT-8870 is a full DTMF
Receiver that integrates both band split filter and decoder
functions into a single 18-pin DIP. Its filter section uses
switched capacitor technology for both the high and low group
filters and for dial tone rejection. Its decoder uses digital
counting techniques to detect and decode all 16 DTMF tone
pairs into a 4-bit code. External component count is minimized
by provision of an on-chip differential input amplifier, clock
generator, and latched tri-state interface bus. Minimal
external components required include a low-cost 3.579545 MHz
crystal, a timing resistor, and a timing capacitor. The
MT-8870-02 can also inhibit the decoding of fourth column
digits.
MT-8870 operating
functions include a band split filter that separates the high
and low tones of the received pair, and a digital decoder that
verifies both the frequency and duration of the received tones
before passing the resulting 4-bit code to the output bus.
The low and high
group tones are separated by applying the dual-tone signal to
the inputs of two 6th order switched capacitor band
pass filters with bandwidths that correspond to the bands
enclosing the low and high group tones.
Figure (F).Block diagram of
IC MT8870
The filter also
incorporates notches at 350 and 440 Hz, providing excellent
dial tone rejection. Each filter output is followed by a
single-order switched capacitor section that smoothes the
signals prior to limiting. Signal limiting is performed by
high gain comparators provided with hysteresis to prevent
detection of unwanted low-level signals and noise. The
MT-8870 decoder uses a digital counting technique to determine
the frequencies of the limited tones and to verify that they
correspond to standard DTMF frequencies. When the detector
recognizes the simultaneous presence of two valid tones (known
as signal condition), it raises the Early Steering flag (ESt).
Any subsequent loss of signal condition will cause ESt to
fall. Before a decoded tone pair is registered, the receiver
checks for valid signal duration (referred to as character-
recognition-condition). This check is performed by an external
RC time constant driven by ESt. A short delay to allow the
output latch to settle, the delayed steering output flag (StD)
goes high, signaling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three state
control input (OE) to logic high. Inhibit mode is enabled by a
logic high input to pin 5 (INH). It inhibits the detection of
1633 Hz.
The output code
will remain the same as the previous detected code. On the M-
8870 models, this pin is tied to ground (logic low).
The input
arrangement of the MT-8870 provides a differential input
operational amplifier as well as a bias source (VREF) to bias
the inputs at mid-rail. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for gain
adjustment.
The internal clock
circuit is completed with the addition of a standard 3.579545
MHz crystal.
The input
arrangement of the MT-8870 provides a differential input
operational amplifier as well as a bias source (VREF) to bias
the inputs at mid-rail. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for gain
adjustment.
The
internal clock circuit is completed with the addition of a
standard 3.579545 MHz crystal.
Figure (D). BLOCK DIAGRAM OF THE
SYSTEM
Figure (D) shows the overall
block diagram of "Device control using the telephone"
construction.
IC
NE 555 timer:
The NE555 is an integrated
circuit that capable of producing accurate timing pulses. This
IC is used as a multivibrater. By using this
IC we can construct two types of multivibrater, monostable and
astable. The monostable multivibrater produces a single pulse
when a triggering pulse is applied to its triggering input.
The astable multivibrater produces a train of pulses depending
on the Resister-Capacitor combination wired around it.
With a monostable operation, the
time delay is controlled by one external resistor and one
capacitor connected between Vcc-Discharge (R), and
Threshold-Ground (C). With an astable operation, the frequency
and pulse width are produced by two external resistors and one
capacitor connected between Vcc-Discharge (R),
Discharge-Threshold (R), and Threshold-Ground (C).
Figure J. IC NE 555
74154 4-16
line decoder/demultiplexer:
IC 74154 is a 4-16
line decoder, it takes the 4 line BCD input and selects
respective output one among the 16 output lines. It is active
low output IC so when any output line is selected it is
indicated by active low signal, rest of the output lines will
remain active high. This 4-line-to-16-line decoder utilizes
TTL circuitry to decode four binary-coded inputs into one of
sixteen mutually exclusive outputs when both the strobe
inputs, G1 and G2, are low. The demultiplexing function is
performed by using the 4 input lines to address the output
line, passing data from one of the strobe inputs with the
other strobe input low. When either strobe input is high, all
outputs are high. These demultiplexer are ideally suited for
implementing high-performance memory decoders.
Figure G. IC 74154 4-16 line
decoder
All inputs are buffered and
input clamping diodes are provided to minimize
transmission-line effects and thereby simplify system design.
TRUTH TABLE:
74126
Tri - State Buffer:
This IC is a tri state buffer
contains four independent gates each of which performs a
non-inverting buffer function. The outputs have the 3-STATE
feature. When control
signal is at high state, the outputs are nothing but the data
present at its input terminals. When control signal is at low
state, the outputs are held at high impedance state. So no
output will be available at the output terminal.
Figure H. IC 74126
IC 7474
D-flip-flop:
IC 7474
is a conventional D-flip-flop IC. This IC consists of two D
flip-flops. These flip-flops are used to latch the data that
present at its input terminal. Each flip-flop
has one data, one clock, one clear, one preset input
terminals.
(Above figure shows a single
D-flip-flop)
IC 7447 BCD -
seven segment decoder:
The DM74LS47 accepts four lines
of BCD (8421) input data, generates their complements
internally and decodes the data with seven AND/OR gates having
open-collector outputs to drive indicator segments directly. Each segment
output is guaranteed to sink 24mA in the ON (LOW) state and
withstand 15V in the OFF (HIGH) state with a maximum leakage
current of 250 mA. Auxiliary inputs provided blanking, lamp
test and cascadable zero-suppression functions.
Figure I. IC 7447 BCD -
seven segment decoder
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